Senior Engineer's PCB Design Best Practices

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Circuit design is a fundamental skill for electronic engineers. However, even a flawless schematic can result in poor performance—or complete failure—if the PCB layout is not optimized. Based on years of engineering experience within our company, the following best practices are summarized to guide PCB design.
Regardless of the EDA tool used, PCB design follows a standard workflow. Adhering to this sequence improves efficiency and reduces errors. This guide uses Protel as a reference due to its widespread use, intuitive interface, and robust simulation capabilities.


1. Schematic Design
Schematic design is a critical preparatory step. Beginners often skip this phase to save time, but this frequently leads to issues. While experienced designers may bypass schematics for simple boards, following a structured approach is essential for complex designs and helps cultivate disciplined practices.
Hierarchical design should ensure all sheets are properly interconnected. Due to software-specific differences, connections may appear intact but lack electrical continuity. Without proper verification using design rule checks (DRC), such issues may go undetected until fabrication—underscoring the importance of a methodical workflow.
As long as electrical connectivity is correct, the schematic itself requires no further elaboration. The following sections focus on key considerations during PCB layout.

2. Board Outline Definition
A closed board outline defines the physical boundary for component placement and routing, and is essential for auto-placement. Precision is critical to avoid mechanical fit issues. Using rounded corners is recommended to prevent injury during handling and reduce mechanical stress. In one instance, switching to rounded corners resolved PCB cracking issues that occurred during product transportation.

3. Component and Net Import
Importing components and nets into the board outline is generally straightforward, but errors may occur. Common issues include missing footprints, netlist mismatches, and unused components or pins. These must be resolved by following error prompts before proceeding.

4. Component Placement
Placement significantly affects product reliability, stability, and electromagnetic compatibility (EMC). The following principles should be observed.
4.1 Placement Order

• Mechanical-critical components (connectors, switches, indicators, power inlets) should be placed first and locked to prevent accidental movement.
• Large or special components (heat-generating devices, transformers, ICs) should be placed next.
• Small components should be placed last.

For high-power designs, heat-generating components such as power transistors and transformers should be placed near the board edge and distributed to promote airflow and heat dissipation. Avoid clustering them or placing them near electrolytic capacitors, as excessive heat can accelerate electrolyte aging.

5. Routing
5.1 General Routing Guidelines

• High-frequency digital traces should be short and narrow.
• Maintain adequate isolation between high-current, high-voltage, and small-signal traces. For a 2 kV withstand voltage, a minimum spacing of 2 mm is recommended; for 3 kV, spacing should exceed 3.5 mm. To prevent creepage, routing slots may be added between high- and low-voltage sections.
• On double-sided boards, traces on opposite layers should be perpendicular, diagonal, or curved to minimize parasitic coupling. Input and output traces should not run parallel; adding a ground trace between them helps reduce feedback.
• Use corners greater than 90°. Avoid 90° or sharper angles to reduce signal reflection and EMI.
• Match trace lengths for address and data buses. Shorter traces may require meandering to meet timing requirements.
• Prefer routing on the solder side for through-hole designs.
• Minimize the use of vias and jumpers.
• For single-sided boards, use larger pads and wider traces. Add teardrops where possible to improve mechanical reliability and solderability.
• Use hatched (grid) copper pours instead of solid fills to reduce outgassing during wave soldering and minimize board warpage due to thermal stress. When using copper pours for ground, consider current direction and distribution rather than filling arbitrarily.
• Keep components and traces away from board edges, especially on paper-based single-sided boards, which are prone to cracking under mechanical stress.
• Design for manufacturability (DFM), testability, and maintainability.

5.2 Grounding and EMC
Ground integrity is critical in analog circuits. Even minor ground noise can be amplified in audio power amplifiers, causing audible degradation. In precision A/D converters, high-frequency noise on the ground can induce temperature drift. A common mitigation technique is to place decoupling capacitors at the four corners of the board, connecting one terminal to the ground plane and the other to mounting holes (which are then connected to the chassis via screws), providing a low-impedance path for high-frequency noise.
EMC is increasingly important. Electromagnetic interference (EMI) typically originates from three sources: signal sources, radiation, and transmission lines. Crystal oscillators, in particular, produce strong harmonics. Effective countermeasures include controlling signal amplitude, grounding the oscillator housing, applying shielding, and using dedicated filter circuits.
5.3 Serpentine Routing
Serpentine routing serves different purposes depending on the application. In motherboards, it is commonly used for clock signals such as PCI Clk and AGP Clk to achieve impedance matching and provide inductive filtering.
For high-speed parallel interfaces such as the Intel Hub Architecture (13 HubLink lines at up to 233 MHz), precise length matching is mandatory to avoid timing skew. Serpentine routing is the standard solution in such cases.
A general rule is to maintain spacing between serpentine segments of at least twice the trace width. In addition to impedance control and filtering, serpentine traces may also serve as inductive elements in RF circuits.

6. Final Adjustments and Refinements
After routing, final adjustments should include text placement, component alignment, trace optimization, and copper pouring. These steps should be deferred until after routing is complete to avoid impacting performance.

• Copper pouring typically refers to filling unused areas with copper. Ground pours are preferred over power pours to reduce short-circuit risks. Guard routing uses two parallel ground traces to isolate sensitive signals.
• When using copper pours as ground planes, ensure the entire ground network is fully connected and verify current paths to avoid unintended floating regions.

7. Netlist Verification
Discrepancies may occasionally arise between the PCB layout and the original schematic. A final netlist comparison is essential before releasing the design for fabrication. Skipping this step risks costly re-spins.

8. Simulation
If time permits, post-layout simulation—especially for high-frequency digital circuits—can identify potential signal integrity and EMC issues early, significantly reducing debugging effort during hardware validation.

Kingsheng PCBA provides end-to-end services from layout design, PCB manufacturing, SMT assembly, to final testing. Contact us for a one-stop, efficient solution tailored to your project needs at www.kingshengpcba.com.