Senior Engineer's PCB Design Guidelines

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I. Routing Overview
Routing is the most critical, detailed, and labor-intensive step in PCB design. It includes single-sided, double-sided, and multi-layer routing. Two methods exist: automatic and interactive. Before auto-routing, pre-route critical nets manually. Avoid parallel input/output traces to prevent reflection; add ground isolation if necessary. Adjacent layers should route perpendicularly to reduce parasitic coupling.
Auto-routing success depends on good placement. Set rules for via count, bend limits, and step size. Use exploratory routing for short nets, then maze routing for global path optimization, allowing re-routing to improve results.
For high-density designs, blind and buried vias save routing channels compared to through-holes.


II. Power & Ground Handling
Poor power/ground design degrades performance. Key measures:

• Add decoupling capacitors between power and ground.
• Widen traces: Ground > Power > Signal. Typical widths: signal 0.2–0.3 mm (min 0.05–0.07 mm), power 1.2–2.5 mm.
• Use wide ground grids for digital circuits (not for analog).
• Use copper pours or dedicated power/ground planes.

III. Mixed-Signal Grounding
Separate digital and analog grounds internally; connect them at a single point near the PCB interface (e.g., connector). Do not merge them inside the board.

IV. Routing on Power/Ground Layers
If signal layers are insufficient, route on power or ground layers—preferably on the power layer to preserve ground plane integrity.

V. Thermal Relief for Large Copper Areas
Use thermal relief pads (cross-shaped) for component leads connected to large copper areas to prevent soldering defects caused by excessive heat dissipation.

VI. Routing Grid System
Set grid based on standard 0.1-inch (2.54 mm) pitch or its integer multiples (e.g., 0.05", 0.025"). A balanced grid density ensures routability without excessive data load.

VII. Design Rule Check (DRC)
Verify:

• Clearances (trace–trace, trace–pad, trace–via, etc.)
• Power/ground trace widths and coupling
• Critical signal handling (shortest length, shielding, I/O separation)
• Separate analog/digital grounds
• Silkscreen and solder mask (no overlap with pads)
• No copper overhang on power/ground planes (risk of shorting)

VIII. Netlist Verification
Always verify netlist consistency between schematic and PCB before fabrication.

IX. Simulation
Perform simulation (especially for high-frequency digital circuits) to reduce debugging time.

X. Frequently Asked Questions (FAQs)
A. Software & Setup

• Use consistent libraries and footprints.
• Set default rules, layer stacks, and CAM outputs.

• Footprint not found: Verify library paths and pin mapping.
• Node mismatch: Ensure schematic and PCB pin names match.
• DRC errors: Check clearances, connectivity, and plane settings.

• Electrolytic capacitor: longer lead (+) or "-" marking on body.
• Tantalum: bar indicates (+).
• Diode: ring indicates cathode.
• Transistors: refer to datasheet for pinout.

• 3.3V → 5V: direct drive often possible; check datasheet.
• 5V → 3.3V: use level shifters.
• ECL ↔ TTL: use dedicated translator ICs.

• Use standard footprints (e.g., axial, radial, SOT, SOIC, etc.).
• Print 1:1 to verify before fabrication.
• Prefer buying components before finalizing footprints.

• Use smaller vias (e.g., 10/20 mil) for signals; larger for power.
• Use thinner PCBs.
• Minimize layer transitions.
• Place ground vias near signal vias for return path continuity.
• Remove unnecessary annular rings on inner layers to avoid broken ground planes.

• Start with board outline (rounded corners recommended).
• Place mechanically constrained components first (connectors, switches, etc.) and lock them.
• Follow placement order: fixed parts → large/heat-sensitive parts → small parts.
• Keep heat-generating components near edges and away from electrolytic capacitors.
• Route traces short and direct; avoid acute angles.
• On double-sided boards, route perpendicular between layers.
• Avoid vias and jumpers where possible.
• Use teardrops for single-sided boards.
• Keep components and traces away from board edges.
• Consider manufacturability, testing, and servicing access.